Optimizing Arm Cortex A76 PPA in TSMC 7nm and Arm IP Portfolio for TSMC 22ULP/ULL Processes

  • Paddy Mamtora, Cadence Design Systems, Inc.,
  • Rupal Gandhi , Arm,
  • T Chan, Pixelworks Inc

Implementing Arm’s latest Cortex-A76 high-performance core on a TSMC 7nm process warranted a fully tuned and optimized flow to achieve the design power, performance, and area (PPA) goals. Cadence and Arm collaborated in creating this flow during the Cortex-A76 processor development. This session will discuss the result of this work, a TSMC N7 Cortex-A76 implementation flow tuned for optimal performance per watt.

TSMC 22nm technology offering consists of two variants – 22ULP & 22ULL. Arm has developed IP optimized to both technology variants. This paper would talk about multiple IP & design optimization facets considered in ensuring optimal SOC PPA across different market segments with focus on IOT segment.

Presentation 1-Optimizing Arm Cortex A76 in TSMC 7nm Using Cadence Implementation Flow. Speakers: Paddy Mamtora (CDNS) and Rupal Gandhi (Arm)

Presentation 2- Optimizing Arm Platform & POP IP to Enable Low Power & Low Voltage Applications on TSMC 22ULP/22ULL Technology. Speakers: T Chan (Pixelworks) and Geetha Rangarajan (Arm)

  • Date:Wednesday, October 17
  • Time:4:30 PM - 5:20 PM
  • Location:Executive Ballroom 210B
  • Session Type:Sponsored Session
  • Room:Executive Ballroom 210B
  • Pass Type:All-Access Pass, Expo Floor Pass
Paddy Mamtora
Cadence Design Systems, Inc.
Rupal Gandhi
T Chan
Pixelworks Inc