Optimizing SoC Functional Safety Mechanisms for Arm-based ISO 26262 Compliant Systems - Sponsored By Arm

  • Diego Botero Galeano, Arteris IP

This session describes how to integrate Arm CPUs and CPU clusters into a SoC with safety goals while maintaining data protection throughout the system. By taking advantage of transaction protection provided by the armv8-R architecture and Arm Cortex-R5 and R7 CPUs, the network-on-chip (NoC) interconnect can protect this information using error-correcting code (ECC) until it is transmitted to its destination. Furthermore, functional safety mechanisms like EEC, parity bit, hardware duplication, and consistency checkers can be implemented throughout the NoC interconnect to augment system diagnostic coverage so that it can attain the ISO 26262 ASIL D safety integrity level.

  • Date:Thursday, October 18
  • Time:3:30 PM - 4:20 PM
  • Location:Executive Ballroom 210D
  • Session Type:Sponsored Session
  • Room:Executive Ballroom 210D
  • Pass Type:All-Access Pass, Expo Floor Pass