A Sign-off Driven Physical Design Flow for Arm Processors with RedHawk Analysis Fusion in IC Compiler II - Sponsored By Synopsys, Inc.

  • Kenneth Chang, Synopsys, Inc.,
  • Annapoorna Krishnaswamy, ANSYS

(Box Lunch Provided) Learn how to maximize design QoR and reduce schedules for Arm processor implementation with early accurate power analysis and optimization for power integrity and reliability within IC Compiler™ II, powered by RedHawk™ Analysis Fusion. We will explore how physical designers can leverage this seamless integration and its ease of use to enable up to 5x turnaround time improvement vs. point tool power integrity fixing flows, including leveraging self-heat analysis for thermal-aware EM checks and RedHawk-SC-big data-enabled SoC power integrity and reliability sign-off solution for advanced nodes. Synopsys Fusion Technology™ delivers this tight integration by transparently transferring data between the place-and-route environment and power integrity analysis.

  • Date:Wednesday, October 17
  • Time:12:30 PM - 1:20 PM
  • Location:Executive Ballroom 210D
  • Session Type:Sponsored Session
  • Room:Executive Ballroom 210D
  • Pass Type:All-Access Pass, Expo Floor Pass
Kenneth Chang
Synopsys, Inc.
Annapoorna Krishnaswamy