Now that the PCI Express® (PCIe®) 4.0 Base Specification is released, and numerous 16GT/s designs are in-flight or entering the market, SoC designers and architects are looking ahead to their next-generation designs. PCI Express 5.0 (32GT/s) and CCIX (25GT/s) require designers to consider and overcome several key challenges including managing datapath width, timing closure, signal integrity, and complex packaging issues. In addition, a close collaboration between system designers, SoC designers, and layout designers becomes important. This session addresses how to accelerate your move to these new high-speed standards that are especially useful for infrastructure/server class products, while managing the latency, throughput, power, and area requirements of Arm®-based and other high-performance SoCs.
Session Keywords: Synopsys