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When Clock, Power, and Reset Domains Collide; and How to Solve It with Static “Multi-Domain Verification” - Sponsored By Mentor, a Siemens Business

  • Joe Hupcey, Mentor Graphics

Interaction of functions spanning multiple independent power, clock, and reset domains can potentially cause catastrophic chip failures. Yet design teams still face several challenges to ensure these domains are working correctly with respect to each other. Although designers usually do a good job partitioning a design into power, clock, and reset domains at the chip level, there is considerable difficulty in understanding how these domains interact with each other at the block or lower levels. Standard verification tools and methods offer no reliable way to analyze the different domains together and to verify their interoperation comprehensively. Power-aware simulation is a good start, but there are too many combinations of power, clock, and reset domains to achieve sufficient coverage with simulation to verify the inter-domain interaction dynamically. The situation is made worse when design teams are integrating multiple legacy or third-party IPs that are unfamiliar and/or have limited-to-zero documentation. Hence, static domain analysis is essential to examine the design space thoroughly. In this presentation we will show how a “Multi-Domain Verification” (MDV) approach built on such a static analysis foundation can successfully address these challenges.

  • Date:Thursday, October 18
  • Time:2:30 PM - 3:20 PM
  • Location:Executive Ballroom 210A
  • Session Type:Sponsored Session
  • Room:Executive Ballroom 210A
  • Pass Type:All-Access Pass, Expo Floor Pass
Speakers
Joe Hupcey
Mentor Graphics