High-Performance CPU Implementation at TSMC N7 Node Using Cadence Innovus Implementation System - Sponsored By Cadence Design Systems, Inc.

  • Zhun Cai, Cadence Design Systems, Inc.,
  • Hanhua Deng, Huawei / Hisilicon

Learn how HiSilicon achieves optimal 7nm performance for its CPU designs. In advanced FinFET nodes, physical implementation becomes more complex than before to push higher performance, especially in CPU design. In this paper, we will introduce some useful methods to address the challenges of 7nm CPU designs using the Innovus Implementation System for improved push power, performance, and area (PPA). We will discuss some techniques for not only handling 7nm process requirements, but also helping to push CPU design performance. For example, in the placement stage, early clock flow (ECF) is one key technique we used in the CPU design to achieve higher performance. With ECF, we improve the frequency by 10%. We will also review clock tree optimization methods (CCOpt™ technology) and the SI prevention methodology for advanced node, especially for 7nm. Finally, we will introduce the Tempus™ signoff ECO technology, showing how it is effective to help us quickly complete final timing closure and improve timing correlation between implementation and signoff tools.

  • Date:Wednesday, October 17
  • Time:1:30 PM - 2:20 PM
  • Location:Executive Ballroom 210B
  • Session Type:Sponsored Session
  • Room:Executive Ballroom 210B
  • Pass Type:All-Access Pass, Expo Floor Pass
Zhun Cai
Cadence Design Systems, Inc.
Hanhua Deng
Huawei / Hisilicon