Unblocking Common Bottlenecks in Automotive SoC Verification

  • Marija Ugarak, HDL Design House,
  • Peter Lewin, Arm

This talk will demonstrate the verification strategy for some of the most typical automotive components, derived from an actual SoC based on a Cortex-M0 platform. We’ll identify the most common bottlenecks of such a verification process and provide extensive information on how to avoid them. Attendees will learn how to reduce the amount of engineering hours invested in planning, implementation, and verification.

  • Date:Tuesday, October 16
  • Time:3:30 PM - 4:20 PM
  • Location:Executive Ballroom 210E
  • Session Type:Conference Session
  • Room:Executive Ballroom 210E
  • Pass Type:All-Access Pass
Marija Ugarak
HDL Design House
Peter Lewin